This invention relates generally to data processing control apparatus, and more particularly to improved arbitration means and methods for controlling and sequencing access by a plurality of requestors to a commonly used unit, channel, or service. The plurality of requestors may typically be a plurality of data processors and the commonly used unit may typically be a memory which is used by each processor. As is well known, the manner in which access is provided between the memory and these processors can have a very significant affect on system performance.
A typical prior art arbitration situation is shown in FIG. 1 which illustrates a plurality of processors P-1 to P-N which provide respective request signals Req-1 to Reg-N that are applied to arbitration circuitry 10 for determining which processor is to be granted access by activating one of the arbitration grant outputs Gr-1 to Gr-N respectively corresponding to request signals Reg-1 to Req-N. Since any or all of the input request signals Req-1 to Req-N can be active at a time, the purpose of the arbitration circuitry 10 is to determine which request is to be serviced next if more than one request is active at the same time.
There are various ways known in the art for designing the arbitration circuitry 10 in FIG. 1 for controlling and sequencing the granting of access in response to the input request signals Req-1 to Req-N. For example, one known arbitration approach involves sequentially polling the request signals in some desired order and grafting access whenever a request signal is found to be activated.
In certain systems, such as in a real-time data processing system, it is important to provide an arbitration approach which maximizes the accessibility by all requesting processors while also providing minimum latency for each individual requesting processor. Known arbitration approaches have not been able to satisfactorily meet these requirements.